Rev. 0.2 / Apr. 2009

4

HMT451S6MMP(R)8C

• VDD=VDDQ=1.5V

• VDDSPD=3.0V to 3.6V

• Fully differential clock inputs (CK, /CK) operation

• Differential Data Strobe (DQS, /DQS)

• On chip DLL align DQ, DQS and /DQS transition with

CK transition

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges of

the clock

• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)

supported

• Programmable additive latency 0, CL-1 and CL-2 sup-

ported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

• BL switch on the fly

• 8 banks

• 8K refresh cycles /64ms

• DDR3 SDRAM Package: JEDEC standard 82ball

FBGA(x4/x8) with support balls

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• Auto Self Refresh supported

• 8 bit pre-fetch

1. Description

This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 2Gb M version. DDR3

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM

series based on 2Gb M ver. provide a high performance 8 byte interface in 67.60mm width form factor of industry stan-

dard. It is suitable for easy interchange and addition.

1.1 Device Features & Ordering Information

1.1.1 Features

1.1.2 Ordering Information

*Information on temperature sensor can be found on the label:

Part Name

Density

Organization

# of

DRAMs

# of

ranks

Materials

HMT451S6MMP8C-S6/G7*

4GB

512Mx64

16

2

Lead free

HMT451S6MMR8C-S6/G7*

4GB

512Mx64

16

2

Halogen free