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HMP351U7AFR8C-S6 Datasheet(PDF) 2 Page - Hynix Semiconductor |
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HMP351U7AFR8C-S6 Datasheet(HTML) 2 Page - Hynix Semiconductor |
2 / 20 page Rev. 0.1 / Mar 2009 2 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS ADDRESS TABLE Y5 (DDR2-667) S6 (DDR2-800) S5 (DDR2-800) Unit Speed @CL3 400 400 400 Mbps Speed @CL4 533 533 533 Mbps Speed @CL5 667 800 800 Mbps Speed @CL6 - 800 800 Mbps CL-tRCD-tRP 5-5-5 6-6-6 5-5-5 tCK Density Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 4GB 512M x 64 2 256Mb x 8 16 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 4GB 512M x 72 2 256Mb x 8 18 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms |
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