HMP351S6AFR8C-Y5 datasheet(7/17 Pages) HYNIX

Part #	HMP351S6AFR8C-Y5

Description	200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A

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Manufacturer	HYNIX [Hynix Semiconductor]

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7 / 17 page

Rev. 1.0 / Dec. 2009

7

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges

and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions

and VIH (ac) to VIL (ac) on the negative transitions.

Parameter

Symbol

Min

Max

Unit

Note

dc Input logic HIGH

VIH(DC)

VREF + 0.125

VDDQ + 0.3

V

dc Input logic LOW

VIL(DC)

-0.30

VREF - 0.125

V

Parameter

Symbol

DDR2 667/800

Unit

Min

Max

AC Input logic HIGH

VIH(AC)

VREF + 0.200

-

V

AC Input logic LOW

VIL(AC)

-VREF - 0.200

V

Symbol

Condition

Value

Units

Notes

VREF

Input reference voltage

0.5 * VDDQ

V1

VSWING(MAX)

Input signal maximum peak to peak swing

1.0

V

1

SLEW

Input signal minimum slew rate

1.0

V/ns

2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

VSWING(MAX)

delta TR

delta TF

VREF - VIL(ac) max

delta TF

Falling Slew =

Rising Slew =

VIH(ac)min - VREF

delta TR

< Figure: AC Input Test Signal Waveform>

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