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HMT125S6BFR8C-G7 Datasheet(PDF) 44 Page - Hynix Semiconductor |
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HMT125S6BFR8C-G7 Datasheet(HTML) 44 Page - Hynix Semiconductor |
44 / 51 page Rev. 0.5 / Sep. 2009 44 HMT164S6BFR6C HMT112S6BFR6C HMT125S6BFR8C *Speed Bin Table Notes* Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); DDR3 1333 Speed Bin DDR3-1333H Unit Note CL - nRCD - nRP 9-9-9 Parameter Symbol min max Internal read command to first data tAA 13.5 20 ns ACT to internal read or write delay time tRCD 13.5 — ns PRE command period tRP 13.5 — ns ACT to ACT or REF command period tRC 49.5 — ns ACT to PRE command period tRAS 36 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) Reserved ns 1,2,3,4,7 CWL = 6, 7 tCK(AVG) Reserved ns 4 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7 CWL = 7 tCK(AVG) Reserved ns 4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,4,7 (Optional) Note 9.10 CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,7 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4 CL = 9 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4 CL = 10 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3 (Optional) ns 5 Supported CL Settings 6, 7, 8, 9 nCK Supported CWL Settings 5, 6, 7 nCK |
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