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8 page 
MPC5607B Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Package pinouts Freescale Semiconductor 8 2.1 176LQFP pin configuration Figure 2. 176 LQFP pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3] PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2] PA[9]/GPIO[9]/E0UC[9]/CS2_1/FAB PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1] PE[13]/GPIO[77]/SOUT_2/E1UC[20] PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX VDD_HV VSS_HV PG[0]/GPIO[96]/CAN5TX/E1UC[23] PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX PH[3]/GPIO[115]/E1UC[5]/CS0_1 PH[2]/GPIO[114]/E1UC[4]/SCK_1 PH[1]/GPIO[113]/E1UC[3]/SOUT_1 PH[0]/GPIO[112]/E1UC[2]/SIN_1 PG[12]/GPIO[108]/E0UC[26]/SOUT_4 PG[13]/GPIO[109]/E0UC[27]/SCK_4 PA[3]/GPIO[3]/E0UC[3]/LIN5TX/CS4_1/EIRQ[0]/ADC1_S[0] PI[13]/GPIO[141]/CS1_3/ADC0_S[21] PI[12]/GPIO[140]/CS0_3/ADC0_S20] PI[11]/GPIO[139]/ANS[19]/SIN_3 PI[10]/GPIO[138]/ADC0_S[18] PI[9]/GPIO[137]/ADC0_S[17] PI[8]/GPIO[136]/ADC0_S[16] PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3] PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7] PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2] PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6] PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1] PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5] PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0] PD[12]/GPIO[60]/CS5_0/E0UC[24]/ADC0_S[4] VDD_HV_ADC1 VSS_HV_ADC1 PB[11]/GPIO[27]/E0UC[3]/CS0_0/ADC0_S[3] PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15] PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14] PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13] PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3] PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2] PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1] VDD_HV_ADC0 VSS_HV_ADC0 LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3] LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9] EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14] EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15] E1UC[18]/SCK_5/GPIO[148]/PJ[4] VDD_HV VSS_HV E1UC[17]/SOUT_5/GPIO[127]/PH[15] E1UC[26]/CS0_3/SOUT_4/GPIO[125]/PH[13] E1UC[27]/CS1_3/SCK_4/GPIO[126]/PH[14] CS0_4/E1UC[30]/GPIO[134]/PI[6] CS1_4/E1UC[31]/GPIO[135]/PI[7] SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5] SCK_3/E1UC[13]/GPIO[100]/PG[4] WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3] SOUT_3/E1UC[11]/GPIO[98]/PG[2] MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2] CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0] WKUP[2]/NMI/E0UC[1]/GPIO[1]/PA[1] CAN5TX/E0UC[17]/GPIO[65]/PE[1] CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8] CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9] EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10] WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0] LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV LIN7RX/WKUP[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9] EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8] CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11] MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10] LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7] LIN6TX/E1UC[15]/GPIO[102]/PG[6] LIN0TX/E0UC[30]/CAN0TX/GPIO[16]/PB[0] CAN0RX/WKUP[4]/LIN0RX/E0UC[31]/GPIO[17]/PB[1] CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9] CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8] LIN5TX/E1UC[25]/GPIO[92]/PF[12] E1UC[28]/LIN1TX/GPIO[38]/PC[6] 176 LQFP Top view Note: Availability of port pin alternate functions depends on product selection. |
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