HYMD264G726D4-H datasheet(4/30 Pages) HYNIX

Part #	HYMD264G726D4-H

Description	184pin Registered DDR SDRAM DIMMs

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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4 / 30 page

Rev. 1.1 /May. 2005

4

184pin Registered DDR SDRAM DIMMs

256MB, 32Mb x 72 ECC Registered DIMM: HYMD232G726D[P]8[M]

FUNCTIONAL BLOCK DIAGRAM

Note :

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained

as shown.

3. DQ/DQS resistors should be 22 Ohms.

4. VDDID strap connections (for memory device VDD,VDDQ) :

STRAP OUT (OPEN) : VDD = VDDQ

STRAP IN (VSS) : VDD ≠ VDDQ

5. SDRAM placement alternates between the back and

front sides of the DIMM.

6. Address and control resistors should be 22 Ohms.

DQ00

DQ01

DQ02

DQ03

DQ04

DQ05

DQ06

DQ07

DM

/CS

DQS

D0

DM

/CS

DQS

D1

DM

/CS

DQS

D2

DM

/CS

DQS

DM

/CS

DQS

DM

/CS

DQS

D5

DM

/CS

DQS

DM

/CS

DQS

D7

DM0

DQS0

DM4

DQS4

DM1

DQS1

DM2

DQS2

DM3

DQS3

DM7

DQS7

DM6

DQS6

DM5

DQS5

/RS0

D3

D6

D4

DM

/CS

DQS

DM8

DQS8

D8

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ08

DQ09

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

VDDSPD

VDD

VREF

VSS

Serial PD

DO-D8

Strap:see Note 4

VDDQ

VDDID

DO-D8

CKO, /CKO------PLL*

* Wire per Clock Loading Table/Wiring Diagram

A0-A13

/RAS

/CAS

CKE0

/WE

RA0-RA13-> : A0->A13 : SDRAMs D0-D8

/RRAS->/RAS : SDRAMs D0-D8

/RCAS->/CAS : SDRAMs D0-D8

RCKEO->CKE : SDRAMs D0-D8

/RWE->/WE : SDRAMs D0-D8

/S0

BA0-BA1

/RS0->/CS : SDRAMs D0-D8

RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D8

R

E

G

I

S

T

E

R

/RESET

/PCK

PCK

A0

A1

A2

SDA

SA0 SA1 SA2

Serial PD

SCL

WP

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