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HYMD232726DP8J-D43 Datasheet(PDF) 1 Page - Hynix Semiconductor |
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HYMD232726DP8J-D43 Datasheet(HTML) 1 Page - Hynix Semiconductor |
1 / 30 page Rev. 1.2 / May. 2005 1 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 184pin Unbuffered DDR SDRAM DIMMs based on 256Mb D ver. (TSOP) FEATURES ADDRESS TABLE Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 128MB 16M x 64 1 16Mb x 16 4 12(A0~A11)/2(BA0,BA1)/9(A0~A8) 8K / 64ms 256MB 32M x 64 1 32Mb x 8 8 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 8K / 64ms 256MB 32M x 72 1 32Mb x 8 9 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 8K / 64ms 512MB 64M x 64 2 32Mb x 8 16 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 8K / 64ms 512MB 64M x 72 2 32Mb x 8 18 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 8K / 64ms PERFORMANCE RANGE Note: 1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below Part Number Suffix -D431 -J -K -H Unit Speed Bin DDR400B DDR333 DDR266A DDR266B - CL - tRCD- tRP 3-3-3 2.5-3-3 2-3-3 2.5-3-3 CK Max Clock Frequency CL=3 200 - - - MHz CL=2.5 166 166 133 133 MHz CL=2 133 133 133 133 MHz This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 400 mil TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 256Mb D ver. based unbuffered DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. • JEDEC Standard 184-pin dual in-line memory module (DIMM) • Two ranks 64M x 72, 64M x 64 and One rank 32M x 72, 32M x 64, 16M x 64 organization •2.6V ± 0.1V VDD and VDDQ Power supply for DDR400, 2.5V ± 0.2V for DDR333 and below • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock operations (CK & /CK) with 133/166/200MHz • DLL aligns DQ and DQS transition with CK transition • Programmable CAS Latency: DDR266(2, 2.5 clock), DDR333(2.5 clock), DDR400(3 clock) • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Edge-aligned DQS with data outs and Center-aligned DQS with data inputs • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial Presence Detect (SPD) with EEPROM • Built with 256Mb DDR SDRAMs in 400 mil TSOP II packages • Lead-free product listed for each configuration (RoHS compliant) |
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