Rev. 1.1 /May. 2005

9

184pin Registered DDR SDRAM DIMMs

512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726DF[P]4N

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol

Test Condition

Speed

Unit

Note

DDR400B

DDR333

IDD0

One bank; Active - Precharge; tRC=tRC(min);

tCK=tCK(min); DQ,DM and DQS inputs changing

twice per clock cycle; address and control inputs

changing once per clock cycle

2270

2090

mA

IDD1

One bank; Active - Read - Precharge; Burst

Length=2; tRC=tRC(min); tCK=tCK(min); address

and control inputs changing once per clock cycle

2450

2450

mA

IDD2P

All banks idle; Power down mode; CKE=Low,

tCK=tCK(min)

830

830

mA

IDD2F

/CS=High, All banks idle; tCK=tCK(min); CKE= High;

address and control inputs changing once per clock

cycle. VIN=VREF for DQ, DQS and DM

1730

1550

mA

IDD3P

One bank active; Power down mode; CKE=Low,

tCK=tCK(min)

920

920

mA

IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;

tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS

inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

1550

1460

mA

IDD4R

Burst=2; Reads; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); IOUT=0mA

3530

3350

mA

IDD4W

Burst=2; Writes; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); DQ, DM and DQS inputs chang-

ing twice per clock cycle

3530

3350

mA

IDD5

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz; distrib-

uted refresh

3050

3050

mA

IDD6

CKE=<0.2V; External clock on; tCK

=tCK(min)

Normal

404

404

mA

Low Power

377

377

mA

IDD7

Four bank interleaving with BL=4 Refer to the follow-

ing page for detailed test condition

5150

4970

mA