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LTC2473IDDTRPBF Datasheet(PDF) 10 Page - Linear Technology

Part # LTC2473IDDTRPBF
Description  Selectable 250sps/1ksps, 16-Bit I2C ?誇 ADCs with 10ppm/째C Max Precision Reference
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2473IDDTRPBF Datasheet(HTML) 10 Page - Linear Technology

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LTC2471/LTC2473
10
24713f
APPLICATIONS INFORMATION
Figure 5. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
The LTC2471/LTC2473 can only be addressed as a slave.
It can only transmit the last conversion result. The serial
clock line, SCL, is always an input to the LTC2471/LTC2473
and the serial data line SDA is bidirectional. Figure 5 shows
the definition of the I2C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NAK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Output Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a
Read Request. If the 7-bit address matches the LTC2471/
LTC2473’saddress(0010100or1010100,dependingonthe
state of the pin A0) the ADC is selected. When the device is
addressed during the conversion state, it does not accept
SDA
SCL
SSr
P
S
tHD(STA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
tr
tf
tr
tf
tHIGH
24713 F05


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