 |
 |
|
| LTC6802-2 |
|
|||||||||||||||||
 LINER
|
| |||||||||||||||||
|
11 page 
LTC6802-2 68022fa operaTion Figure 1. 96-Cell Battery Stack, Isolated Interface. In this Diagram the Battery Negative is Isolated from Module Ground. Opto-Couplers or Digital Isolators Allow Each IC to be Addressed Individually. This is a Simplified Schematic Showing the Basic Multi-IC Architecture V2– OE2 V2– V2+ V1– OE1 V1– V1+ DIGITAL ISOLATOR BATTERY POSITIVE 350V 3V 3V MODULE IO ADDRESS 0 V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 CSBI SDO SDI SCKI A3 A2 A1 A0 GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V– S1 C1 S2 LTC6802-2 IC #1 MISO CS MOSI CLK MPU 68022 F01 V2– OE2 V2– V2+ V1– OE1 V1– V1+ DIGITAL ISOLATOR 3V ADDRESS 1 V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 CSBI SDO SDI SCKI A3 A2 A1 A0 GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V– S1 C1 S2 LTC6802-2 IC #2 V2– OE2 V2– V2+ V1– OE1 V1– V1+ DIGITAL ISOLATOR 3V ADDRESS 15 V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 CSBI SDO SDI SCKI A3 A2 A1 A0 GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V– S1 C1 S2 LTC6802-2 IC #8 IC #3 TO IC #7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + between C2 and C4 after several cycles of measuring cells B3 and B4. Thus the measurements for B3 and B4 may indicate a valid cell voltage when in fact the exact state of B3 and B4 is unknown. To reliably detect an open connection, the command STOWAD is provided. With this command, two 100µA current sources are connected to the ADC inputs and turned on during all cell conversions. Referring again to Figure 3, with the STOWAD command, the C3 pin will be pulled down by the 100µA current source during the B3 cell measurement AND during the B4 cell measurement. This will tend to decrease the B3 measurement result and increase the B4 measurement result relative to the normal STCVAD command. The biggest change is observed in the |
|
