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LTC4355CMSTRPBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC4355CMSTRPBF Datasheet(HTML) 9 Page - Linear Technology |
9 / 20 page LTC4355 9 4355fe APPLICATIONS INFORMATION System Power Supply Failure The LTC4355 automatically supplies load current from the system input supply with the higher voltage. If this supply shorts to ground, reverse current begins to flow through the pass transistor temporarily and the transistor begins to turn off. When this reverse current creates –25mV of voltage drop across the drain and source pins of the pass transistor, a fast pull-down circuit engages to drive the gate low faster. The remaining system power supply delivers the load cur- rent through the body diode of its pass transistor until the channel turns on. The LTC4355 ramps the gate up with 20μA, turning on the N-channel MOSFET to reduce the voltage drop across it. Input Short-Circuit Faults The dynamic behavior of an active, ideal diode entering reverse bias is most accurately characterized by a delay followed by a period of reverse recovery. During the delay phase some reverse current is built up, limited by para- sitic resistances and inductances. During the reverse re- covery phase, energy stored in the parasitic inductances is transferred to other elements in the circuit. Current slew rates during reverse recovery may reach 100A/μs or higher. High slew rates coupled with parasitic inductances in se- ries with the input and output paths may cause potentially destructive transients to appear at the IN and OUT pins of the LTC4355 during reverse recovery. A zero impedance short-circuit directly across an input that is supplying current is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. When the MOSFET finally commutates the reverse current the LTC4355 IN pin experiences a nega- tive voltage spike, while the OUT pin spikes in the positive direction. To prevent damage to the LTC4355 under conditions of input short-circuit, protect the IN pins and OUT pin as shown in Figure 1. The IN pins are protected by clamping to the GND pin in the negative direction. Protect the OUT pin with a clamp, such as with a TVS or TransZorb, or with a local bypass capacitor of at least 10μF. In low voltage applications the MOSFET’s drain-source breakdown may be sufficient to protect the OUT pin, provided BVDSS + VIN < 100V. Parasitic inductance between the load bypass or the second supply and the LTC4355 allows a zero impedance input short to collapse the voltage at the OUT pin, which increases the total turn-off time (tOFF). For applications up to 30V, bypass the OUT pin with 39μF; above 30V use at least 100μF. One capacitor serves to guard against OUT collapse and also protect OUT from voltage spikes. Figure 1. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pins. The Polarity of Step Recovery Spikes Is Shown Across Parasitic Inductances LTC4355 GND GATE1 GATE2 IN1 OUT IN2 M1 FDS3672 REVERSE RECOVERY CURRENT M2 FDS3672 VIN1 VOUT VIN2 DIN2 SBR1U150SA INPUT PARASITIC INDUCTANCE + – OUTPUT PARASITIC INDUCTANCE + – INPUT PARASITIC INDUCTANCE – + COUT 10μF CLOAD DCLAMP SMAT70A OR REVERSE RECOVERY CURRENT 4355 F01 DIN1 SBR1U150SA INPUT SHORT |
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