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LTC3890EGN-1TRPBF Datasheet(PDF) 8 Page - Linear Technology |
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LTC3890EGN-1TRPBF Datasheet(HTML) 8 Page - Linear Technology |
8 / 36 page LTC3890-1 8 38901f PIN FUNCTIONS ITH1, ITH2 (Pin 1, Pin 13): Error Amplifier Outputs and Switching Regulator Compensation Points. Each associ- ated channel’s current comparator trip point increases with this control voltage. VFB1, VFB2 (Pin 2, Pin 12): Receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. SENSE1+, SENSE2+ (Pin 3, Pin 11): The (+) input to the differential current comparators are normally connected to DCR sensing networks or current sensing resistors. The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE1–, SENSE2– (Pin 4, Pin 10): The (–) Input to the Differential Current Comparators. When greater than INTVCC – 0.5V, the SENSE– pin supplies current to the current comparator. FREQ (Pin 5): The Frequency Control Pin for the Internal VCO. Connecting the pin to GND forces the VCO to a fixed low frequency of 350kHz. Connecting the pin to INTVCC forces the VCO to a fixed high frequency of 535kHz. Other frequencies between 50kHz and 900kHz can be programmed using a resistor between FREQ and GND. An internal 20μA pull-up current develops the voltage to be used by the VCO to control the frequency. PLLIN/MODE (Pin 6): External Synchronization Input to Phase Detector and Forced Continuous Mode Input. When an external clock is applied to this pin, the phase-locked loop will force the rising TG1 signal to be synchronized with the rising edge of the external clock. When not syn- chronizing to an external clock, this input, which acts on both controllers, determines how the LTC3890-1 operates at light loads. Pulling this pin to ground selects Burst Mode operation. An internal 100k resistor to ground also invokes Burst Mode Operation when the pin is floated. Tying this pin to INTVCCforcescontinuousinductorcurrentoperation. Tying this pin to a voltage greater than 1.2V and less than INTVCC – 1.3V selects pulse skipping operation. SGND (Pin 7): Small-signal ground common to both controllers, must be routed separately from high current grounds to the common (–) terminals of the CIN capaci- tors. RUN1, RUN2 (Pin 8, Pin 9): Digital Run Control Inputs for Each Controller. Forcing either of these pins below 1.2V shuts down that controller. Forcing both of these pins below 0.7V shuts down the entire LTC3890-1, reducing quiescent current to approximately 14μA. INTVCC (Pin19): Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7μF ceramic or other low ESR capacitor. Do not use the INTVCC pin for any other purpose. EXTVCC (Pin 20): External Power Input to an Internal LDO Connected to INTVCC. This LDO supplies INTVCC power, bypassing the internal LDO powered from VIN whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 14V on this pin. PGND (Pin 21): Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs and the (–) terminal(s) of CIN. VIN (Pin 22): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. |
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