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LTC4070EMS8EPBF Datasheet(PDF) 11 Page - Linear Technology

Part # LTC4070EMS8EPBF
Description  Li-Ion/Polymer Shunt Battery Charger System
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4070EMS8EPBF Datasheet(HTML) 11 Page - Linear Technology

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LTC4070
11
4070f
APPLICATIONS INFORMATION
points are found by looking up the curve 1 thermistor R/T
values plus RFIX that correspond to the ratios for NTCTH1
= 36.5%, NTCTH2 = 29.0%, NTCTH3 = 22.8%, and NTCTH4
= 17.8%. Selecting RFIX = 3.92k results in trip points of
39.9°C, 49.4°C, 59.2°C and 69.6°C.
Another technique may be used without adding an ad-
ditional component. Instead decrease RNOM to adjust the
NTCTH thresholds for a given R/T thermistor profile. For
example, if RNOM = 88.7k (with the same 100k curve 1
thermistor) then the temperature trip points are 41.0°C,
49.8°C, 58.5°C, and 67.3°C.
When using the NTC features of the LTC4070 it is important
to keep in mind that the maximum shunt current increases
as the float voltage, VFLOAT_EFFdropswithNTCconditioning.
Reviewing the Typical Application with a 12V wall adapter
in Figure 1; the input resistor, RIN, should be increased
to 165Ω such that the maximum shunt current does not
exceed 50mA at the lowest possible float voltage due to
NTC conditioning, VFLOAT_MIN = 3.8V.
Thermal Considerations
At maximum shunt current, the LTC4070 may dissipate up
to 205mW. The thermal dissipation of the package should
be taken into account when operating at maximum shunt
current so as not to exceed the absolute maximum junc-
tion temperature of the device. With
θJA of 40°C/W, in the
MSOP package, at maximum shunt current of 50mA the
junction temperature rise is about 8°C above ambient.
With
ΘJA of 76°C/W in the DFN package, at maximum
shunt current of 50mA the junction temperature rise is
about 16°C above ambient.
Operation with an External PFET To Boost Shunt
Current
Table 2 lists recommended devices to increase the
maximum shunt current. Due to the requirement for low
capacitance on the DRV pin node, it is recommended that
only low gate charge and high threshold PFET devices be
used. Also it is recommended that careful PCB layout be
used to keep leakage at the DRV pin to a minimum as the
IDRV(SINK) current is typically 3μA.
Refer to device manufacturers data sheets for maximum
continuous power dissipation and thermal resistance when
selecting an external PFET for a particular application.
Table 2. Recommended External Shunt PFETS
DEVICE
VENDOR
QGS
VTH(MIN)
RDS(ON)
FDN352AP
Fairchild
0.50nC
–0.8V
0.33
Si3467DV
Vishay
1.7nC
–1.0V
0.073
Si3469DV
Vishay
3.8nC
–1.0V
0.041
DMP2130LDM
Diodes Inc.
2.0nC
–0.6V
0.094
DMP3015LSS
Diodes Inc.
7.2nC
–1.0V
0.014


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