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LTC4070EMS8E Datasheet(PDF) 7 Page - Linear Technology |
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LTC4070EMS8E Datasheet(HTML) 7 Page - Linear Technology |
7 / 16 page LTC4070 7 4070f BLOCK DIAGRAM 4070 BD 3-STATE DETECT OSC CLK ADJ 1.5s PULSED DUTY CYCLE < 0.002% 30μs NTCBIAS NTC RNOM 10k T – + – + REF – + EA GND DRV HBO LBO VCC ADC NTHS0805N02N1002J LTC4070 OPERATION The LTC4070 provides a simple, reliable, and high perfor- mance battery protection and charging solution by prevent- ing the battery voltage from exceeding a programmed level. Its shunt architecture requires just one resistor between the input supply and the battery to handle a wide range of battery applications. When the input supply is removed and the battery voltage is below the high battery output threshold, the LTC4070 consumes just 450nA from the battery. While the battery voltage is below the programmed float voltage, the charge rate is determined by the input voltage, the battery voltage, and the input resistor: ICHG = VIN − VBAT () RIN As the battery voltage approaches the float voltage, the LTC4070 shunts current away from the battery thereby reducing the charge current. The LTC4070 can shunt up to 50mA with float voltage accuracy of ±1% over temperature. The shunt current limits the maximum charge current, but the 50mA internal capability can be increased by adding an external P-channel MOSFET. Adjustable Float Voltage, VFLOAT A built-in 3-state decoder connected to the ADJ pin provides three programmable float voltages: 4.0V, 4.1V, or 4.2V. The float voltage is programmed to 4.0V when ADJ is tied to GND, 4.1V when ADJ is floating, and 4.2V when ADJ is tied to VCC. The state of the ADJ pin is sampled about once every 1.5 seconds. When it is being sampled, the LTC4070 applies a relatively low impedance voltage at the ADJ pin. This technique prevents low level board leakage from corrupting the programmed float voltage. |
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