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LT3686IDDTRPBF Datasheet(PDF) 10 Page - Linear Technology |
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LT3686IDDTRPBF Datasheet(HTML) 10 Page - Linear Technology |
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10 / 28 page  LT3686 0 3686fa Input Voltage Range TheinputvoltagerangefortheLT3686applicationsdepends ontheoutputvoltageandontheabsolutemaximumratings of the VIN and BOOST pins. The minimum input voltage is determined by either the LT3686’s minimum operating voltage of 3.6V, or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: DC = VOUT + VD VIN – VSW + VD Where VD is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.67V at maximum load). This leads to a minimum input voltage of: VIN(MIN)= VOUT + VD DCMAX – VD + VSW DCMAX can be adjusted with frequency. The boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to sustain the charge across the boost capacitor. ApplicAtions inForMAtion FB Resistor Network The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resis- tors according to: R1=R2 VOUT 0.8V – 1 ⎛ ⎝⎜ ⎞ ⎠⎟ R2 should be 20k or less to avoid bias current errors. Reference designators refer to the Block Diagram. Programmable Undervoltage Lockout The EN/UVLO pin can be programmed by an external re- sistor divider between VIN and the EN/UVLO pin. Choose the resistors according to: R4 =R5 VIN 1.27V – 1 R4 also sets the hysteresis voltage for the programmable UVLO: Hysteresis = R4 • 2.4µA OnceVINdropsbelowtheprogrammedvoltage,theLT3686 will enter a low quiescent current state (IQ ≈ 15µA). To shutdown the LT3686 completely (IQ < 2µA), reduce EN/ UVLO pin voltage to below 0.4V. Figure 1. IQ vs VEN/UVLO (VIN = 10V) Figure 2. EN/UVLO Pin Current EN/UVLO (V) 1 10 1000 100 0 1 2 3 4 5 6 7 3686 F01 0.1 10000 8 EN/UVLO (V) 5 10 20 25 30 35 40 15 0 10 20 30 40 50 3686 F02 0 45 |
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