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AD6659-80EBZ Datasheet(PDF) 7 Page - Analog Devices |
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AD6659-80EBZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 40 page AD6659 Rev. | Page 7 of 40 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter Temp Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 480 MHz Conversion Rate1 Full 3 80 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 ns CLK Pulse Width High (tCH) Full 6.25 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 ns DCO Propagation Delay (tDCO) Full 3 ns DCO to Data Skew (tSKEW) Full 0.1 ns Pipeline Delay (Latency) Full 9 Cycles With NSR Enabled Full 10 Cycles With QEC Enabled Full 11 Cycles Wake-Up Time2 Full 350 μs Standby Full 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. tPD tSKEW tCH tDCO tCLK N – 9 N – 1 N + 1 N + 2 N + 3 N + 5 N + 4 N N – 8N – 7N – 6N – 5 VIN CLK+ CLK– CH A/CH B DATA DCOA/DCOB tA Figure 2. CMOS Output Data Timing |
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