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NCP1380 Datasheet(PDF) 4 Page - ON Semiconductor |
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NCP1380 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 26 page NCP1380 http://onsemi.com 4 INTERNAL CIRCUIT ARCHITECTURE FB Ct ICt + − + − ZCD La ux 10 V ESD Vth DRV de ma g S R Q CS Rsense LEB 1 / 4 VDD VDD Soft-start VCC aux V CC management latch VDD Rpullup fa ul t DRV ga te gr a nd reset gr a nd reset gr a nd reset DRV clamp Soft−s ta rt e nd ? the n 1 else 0 A: l a tc he d IpFlag + − SS end IpFlag PWMreset P W Mr eset GN D Up Down TIM ER Reset VCCstop BO r eset L OGI C BL OCK VDD Fa ul t VCC VOVP IOTP(REF) OPP VILIMIT VDD VOTP SS end noi s e de l a y noi s e de l a y 5 ms Ti me Out LEB 2 + − VC S(stop) CsS top Cs S top LEB 2 is shorter than LEB 1 40 ms Ti me Out SS end The 40 ms Time Out is active only during s oft−sta r t SS end Figure 3. Internal Circuit Architecture for Versions A and B S R Q Q Q Ipeak(VCO) = 17.5% VILIMIT Ct s e tpoi nt Ct Discharge 3 ms blanking |
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