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MAX11048ETN+ Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX11048ETN+ Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 18 page 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs _______________________________________________________________________________________ 9 Pin Description PIN NAME FUNCTION 1 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 2 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 3 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 4 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 5 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 6 DB8 16-Bit Parallel Data Bus Digital Output Bit 8 7, 21, 50 DGND Digital Ground 8, 20, 51 DVDD Digital Supply. Bypass to DGND with a 0.1μF capacitor at each DVDD input. 9 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 10 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 11 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 12 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 13 DB3 16-Bit Parallel Data Bus Digital I/O Bit 3 14 DB2 16-Bit Parallel Data Bus Digital I/O Bit 2 15 DB1 16-Bit Parallel Data Bus Digital I/O Bit 1 16 DB0 16-Bit Parallel Data Bus Digital I/O Bit 0 17 EOC Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. 18 CONVST Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode is zero. 19 SHDN Active-High Shutdown Input. Drive the SHDN high to place the device into a low-current state. In shutdown mode, the contents of the configuration register are not lost. 22, 28, 35, 43, 49 RDC Reference Buffer Decoupling. Bypass to AGND with at least a 22μF capacitor each at pins 22, 28, 43, and 49. Connect all RDC outputs together and bypass with 80μF total capacitance. See the Layout, Grounding, and Bypassing section. 23, 27, 33, 38, 44, 48 AGNDS Signal Ground. Connect all AGND and AGNDS inputs together. 24, 30, 41, 47 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1μF capacitor at each AVDD input. 25, 31, 40, 46 AGND Analog Ground. Connect all AGND inputs together. 26 CH0 Channel 0 Analog Input for the MAX11049 29 CH1 Channel 1 Analog Input for the MAX11049. Channel 0 for the MAX11048. 32 CH2 Channel 2 Analog Input for MAX11049. Channel 1 for the MAX11048, Channel 0 for the MAX11047. 34 CH3 Channel 3 Analog Input for MAX11049. Channel 2 for the MAX11048, Channel 1 for the MAX11047. 36 REFIO External Reference Input/Internal Reference Output. Place a 0.1μF capacitor from REFIO to AGND. 37 CH4 Channel 4 Analog Input for the MAX11049. Channel 3 for the MAX11048, Channel 2 for the MAX11047. 39 CH5 Channel 5 Analog Input for the MAX11049. Channel 4 for the MAX11048, Channel 3 for the MAX11047. |
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