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T T TS S S2 2 2G G G~ ~ ~1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc. V1.1 28 True IDE Multiword DMA Mode Read/Write Timing Specification The timing diagram for True IDE DMA mode of operation in this section is drawn using the conventions in the ATA-4 specification. Signals are shown with their asserted state as high regardless of whether the signal is actually negative or positive true. Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the diagram inverted from their electrical states on the bus. Item Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Mode 3 (ns) Mode 4 (ns) Note tO Cycle time (min) 480 150 120 100 80 1 tD -IORD / -IOWR asserted width (min) 215 80 70 65 55 1 tE -IORD data access (max) 150 60 50 50 45 tF -IORD data hold (min) 5 5 5 5 5 tG -IORD/-IOWR data setup (min) 100 30 20 15 10 tH -IOWR data hold (min) 20 15 10 5 5 tI DMACK to –IORD/-IOWR setup (min) 0 0 0 0 0 tJ -IORD / -IOWR to -DMACK hold (min) 20 5 5 5 5 tKR -IORD negated width (min) 50 50 25 25 20 1 tKW -IOWR negated width (min) 215 50 25 25 20 1 tLR -IORD to DMARQ delay (max) 120 40 35 35 35 tLW -IOWR to DMARQ delay (max) 40 40 35 35 35 tM CS(1:0) valid to –IORD / -IOWR 50 30 25 10 5 tN CS(1:0) hold 15 10 10 10 10 tZ -DMACK 20 25 25 25 25 |
