Detailed Description

The MAX1393/MAX1396 use an input track and hold

(T/H) circuit along with a SAR to convert an analog input

signal to a serial 12-bit digital output data stream. The

serial interface provides easy interfacing to microproces-

sors and DSPs. Figure 3 shows the simplified functional

diagram for the MAX1393 (1 channel, true differential)

and the MAX1396 (2 channels, single ended).

True-Differential Analog Input T/H

The equivalent input circuit of Figure 4 shows the

MAX1393/MAX1396 input architecture, which is com-

posed of a T/H, a comparator, and a switched-capacitor

DAC. The T/H enters its tracking mode on the falling

edge of CS (while OE is held low). The positive input

capacitor is connected to AIN+ (MAX1393), or to AIN1 or

AIN2 (MAX1396). The negative input capacitor is con-

nected to AIN- (MAX1393) or GND (MAX1396). The T/H

enters its hold mode on the 3rd falling edge of SCLK

8

_______________________________________________________________________________________

1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 12-Bit, SAR ADCs

PIN

MAX1393

MAX1396

NAME

FUNCTION

1

1

with a 0.1μF capacitor as close to the device as possible.

2

—

AIN-

Negative Analog Input

—

2

AIN2

Analog Input Channel 2

3

—

AIN+

Positive Analog Input

—

3

AIN1

Analog Input Channel 1

4

4

GND

Ground

5

5

REF

0.1μF capacitor as close to the device as possible.

6

—

UNI/

BIP

Input-Mode Select. Drive UNI/

BIP high to select unipolar input mode. Pull UNI/BIP low to

select bipolar input mode. In unipolar mode, the output data is in straight binary format. In

bipolar mode, the output data is in two’s complement format.

—

6

CH1/CH2

Channel-Select Input. Pull

CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select

channel 2.

7

7

OE

Active-Low Output Enable. Pull

OE low to enable DOUT. Drive OE high to disable DOUT.

Connect to

CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface

with DSP devices.

8

8

CS

Active-Low Chip-Select Input. A falling edge on

CS initiates power-up and acquisition.

9

9

DOUT

Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high

impedance when

OE is high.

10

10

SCLK

Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition

ends on the 3rd falling edge after the

CS falling edge. The LSB is clocked out on the SCLK

15th falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).

—

—

EP

Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave unconnected.

Pin Description

DOUT

REF

12-BIT SAR

ADC

CS

SCLK

OE

GND

OUTPUT

SHIFT

REGISTER

CONTROL

LOGIC AND

TIMING

*INDICATES THE MAX1396

AIN+ (AIN1)*

AIN- (AIN2)*

INPUT

MUX

AND T/H

UNI/BIP

(CH1/CH2)*

MAX1393

MAX1396

Figure 3. Simplified Functional Diagram