AD9575ARUZLVD datasheet(4/16 Pages) AD

Part #	AD9575ARUZLVD

Description	Network Clock Generator, Two Outputs

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Manufacturer	AD [Analog Devices]

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AD9575

Rev. 0 | Page 4 of 16

LVDS

LVCMOS

LVPECL

Parameter

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

PLL Noise (312.5 MHz Output)

At 1 kHz

−112

dBc/Hz

At 10 kHz

−119

dBc/Hz

At 100 kHz

−120

dBc/Hz

At 1 MHz

−140

−142

dBc/Hz

At 10 MHz

−152

−154

dBc/Hz

At 30 MHz

−153

−155

dBc/Hz

PLL Noise (33.33 MHz Output)

At 1 kHz

−131

dBc/Hz

At 10 kHz

−138

dBc/Hz

At 100 kHz

−140

dBc/Hz

At 1 MHz

−155

dBc/Hz

At 5 MHz

−155

dBc/Hz

PLL Noise (62.5 MHz Output)

At 1 kHz

−126

dBc/Hz

At 10 kHz

−133

dBc/Hz

At 100 kHz

−134

dBc/Hz

At 1 MHz

−150

dBc/Hz

At 5 MHz

−152

dBc/Hz

Spurious Content

−70

dBc

PLL Figure of Merit

−217

dBc/Hz

LVDS CLOCK OUTPUT JITTER (TYP/MAX)

Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 2.

Jitter Integration Bandwidth

100 MHz

106.25 MHz

125 MHz

155.52 MHz

156.25 MHz

159.375 MHz

312.5 MHz

Unit

12 kHz to 20 MHz

0.38/0.50

0.40/0.54

0.37/0.47

0.41/0.54

0.39/0.51

0.38/0.51

0.36/0.48

ps rms

1.875 MHz to 20 MHz

0.15/0.27

ps rms

0.637 MHz to 10 MHz

0.15/0.21

ps rms

LVPECL CLOCK OUTPUT JITTER (TYP/MAX)

Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 3.

Jitter Integration Bandwidth

100 MHz

106.25 MHz

125 MHz

155.52 MHz

156.25 MHz

159.375 MHz

312.5 MHz

Unit

12 kHz to 20 MHz

0.36/0.46

0.44/0.68

0.36/0.45

0.40/0.52

0.39/0.64

0.41/0.62

0.38/0.49

ps rms

1.875 MHz to 20 MHz

0.19/0.54

ps rms

0.637 MHz to 10 MHz

0.22/0.35

ps rms

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AD9575ARUZLVD Datasheet(PDF) 4 Page - Analog Devices

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