NJG1665MD7

- 6 -

■ APPLICATION CIRCUIT

PARTS LIST

■ TEST PCB LAYOUT

(TOP VIEW)

PRECAUTIONS

[1] The DC blocking capacitors should be placed at RF terminal of P1, P2, P3, P4, P5 and PC.

Please choose appropriate capacitance values to the application frequency.

[2] The bypass capacitor (C7) should be placed as close as possible to VDD terminal.

[3] For good RF performance, all GND terminals are should be connected to PCB ground plane.

Part ID

Value

Notes

C1~C6

56pF

C7

1000pF

MURATA MFG

(GRM15)

(Top view)

4

5

6

12

11

10

8

13

7

9

14

1

2

3

DECODER

PC

P1

P2

P3

P4

P5

VDD

CTL1

CTL2

CTL3

C1

56pF

C2

56pF

C3

56pF

C4

56pF

C5

56pF

C6

56pF

C7

1000pF

PCB SIZE=39.0 x 20.0mm

PCB: FR-4, t=0.2mm

CAPACITOR: size 1005

STRIP LINE WIDTH=0.4mm

Losses of PCB and Connectors

Loss (dB)

Freq.

(GHz)

PC-P1

PC-P5

PC-P2

PC-P4

PC-P3

1.0

0.41

0.43

0.36

2.0

0.62

0.65

0.52

2.5

0.74

0.79

0.61

P3

P2

P4

P5

P1

PC

C1

C2

C3

C4

C5

C6

C7

1pin mark

GND

GND