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CY8CLED02
Document Number: 001-13704 Rev. *C
Page 10 of 39
Register Reference
Register Conventions
This section lists the registers of the CY8CLED02 EZ-Color
device.
The register conventions specific to this section are listed in the
following table.
Register Mapping Tables
The device has a total register address space of 512 bytes. The
register space is referred to as I/O space and is divided into two
banks. The XOI bit in the Flag register (CPU_F) determines
which bank the user is currently in. When the XOI bit is set the
user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Table 6. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 7. Register Map Bank 0: User Space
PRT0DR
00
RW
40
ASE10CR0
80
RW
C0
PRT0IE
01
RW
41
81
C1
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
C3
PRT1DR
04
RW
44
ASE11CR0
84
RW
C4
PRT1IE
05
RW
45
85
C5
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
08
48
88
C8
09
49
89
C9
0A
4A
8A
CA
0B
4B
8B
CB
0C
4C
8C
CC
0D
4D
8D
CD
0E
4E
8E
CE
0F
4F
8F
CF
10
50
90
D0
11
51
91
D1
12
52
92
D2
13
53
93
D3
14
54
94
D4
15
55
95
D5
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
I2C_MSCR D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
DC
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
DF
DBB00DR0
20
#
AMX_IN
60
RW
A0
INT_MSK0
E0
RW
DBB00DR1
21
W
61
A1
INT_MSK1
E1
RW
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
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