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ADC1413D065HN Datasheet(PDF) 11 Page - NXP Semiconductors |
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ADC1413D065HN Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 38 page ADC1413D065_080_105_125_2 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 02 — 4 June 2009 11 of 38 NXP Semiconductors ADC1413D065/080/105/125 Dual 14 bits ADC; 65, 80, 105 or 125 Msps • 3.125 Gbps data rate • Tamb =25˚C • DC coupling with 2 different receiver common-mode voltages. 12. SPI timing Fig 3. Eye diagram at 1 V receiver common mode Fig 4. Eye diagram at 2 V receiver common mode 005aaa088 005aaa089 Table 8. Characteristics Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 °C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Serial Peripheral Interface timings tw(SCLK) SCLK pulse width 40 ns tw(SCLKH) SCLK pulse width HIGH 16 ns |
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