Detailed Description

The MAX9312/MAX9314 are low-skew, dual 1-to-5 differ-

ential drivers designed for clock and data distribution.

For interfacing to differential HSTL and LVPECL signals,

these devices operate over a +2.25V to +3.8V supply

range, allowing high-performance clock or data distribu-

tion in systems with a nominal +2.5V or +3.3V supply.

For differential LVECL operation, these devices operate

from a -2.25V to -3.8V supply.

The differential inputs can be configured to accept sin-

to 3.8V for the MAX9314. This is accomplished by con-

as a reference. For example, the differential CLKA, CLKA

input is converted to a noninverting, single-ended input

ended input to CLKA. Similarly, an inverting input is

the single-ended input to CLKA. With a differential input

gle-ended LVPECL/LVECL signal.

When a differential input is configured as a single-ended

2.7V to 3.8V for the MAX9314. This is because one of the

because it becomes the high-level input when the other

(single-ended) input swings below it. Therefore, mini-

supply of 2.725V for the MAX9312 and 2.58V for the

MAX9314. Rounding up to standard supplies gives the

3.8V for the MAX9314.

source or sink 0.5mA, which is sufficient to drive two

The maximum magnitude of the differential input from

This limit also applies to the difference between any ref-

erence voltage input and a single-ended input.

The differential inputs have bias resistors that drive the

outputs to a differential low when the inputs are open.

The inverting inputs (CLKA and CLKB) are biased with a

75k

noninverting inputs (CLKA and CLKB) are biased with a

75k

Specifications for the high and low voltages of a differen-

tial input of at least 95mV switches the outputs to the

Characteristics table.

Applications Information

Supply Bypassing

ceramic 0.1µF and 0.01µF capacitors in parallel as close

to the device as possible, with the 0.01µF value capaci-

tor closest to the device. Use multiple parallel vias for

Traces

Input and output trace characteristics affect the perfor-

mance of the MAX9312/MAX9314.

Connect each signal of a differential input or output to a

50

Ω characteristic impedance trace. Minimize the num-

ber of vias to prevent impedance discontinuities. Reduce

reflections by maintaining the 50

Ω characteristic imped-

ance through connectors and across cables. Reduce

skew within a differential pair by matching the electrical

length of the traces.

Output Termination

Terminate outputs through 50

equivalent Thevenin termination. When a single-ended

signal is taken from a differential output, terminate both

outputs. For example, if QA0 is used as a single-ended

output, terminate both QA0 and QA0.

Dual 1:5 Differential LVPECL/LVECL/HSTL

Clock and Data Drivers

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