when using the internal reference. Bypass REFO to

GND with a 47pF (maximum 100pF) capacitor.

Alternatively, if heavier decoupling is required, use a

1k

Ω resistor in series with a 1µF capacitor in parallel

with the existing 100pF capacitor. REFO can deliver up

to 100µA of current with no degradation in perfor-

mance. Configure other reference voltages by applying

a resistive potential divider with a total resistance

greater than 33k

Ω from REFO to GND.

External Reference

The external reference input features a typical input

impedance of 113k

Ω and accepts an input voltage

from +2V to AVDD. Connect an external voltage

supply between REFI and GND to apply an ex-

ternal reference. Leave REFO unconnected. Visit

available external voltage-reference devices.

AVDD as Reference

Connect AVDD to REFI to use AVDD as the reference

voltage. Leave REFO unconnected.

Serial Interface

The MAX5134–MAX5137 3-wire serial interface is com-

patible with MICROWIRE, SPI, QSPI, and DSPs (Figures

2, 3). The interface provides three inputs, SCLK, CS,

and DIN and one output, READY. Use READY to verify

communication or to daisy-chain multiple devices (see

the READY section). READY is capable of driving a

20pF load with a 30ns (max) delay from the falling edge

of SCLK. The chip-select input (CS) frames the serial

data loading at DIN. Following a chip-select input’s

high-to-low transition, the data is shifted synchronously

and latched into the input register on each falling edge

of the serial-clock input (SCLK). Each serial word is 24

bits. The first 8 bits are the control word followed by 16

data bits (MSB first), as shown in Table 1. The serial

input register transfers its contents to the input registers

after loading 24 bits of data. To initiate a new data

transfer, drive CS high, keep CS high for a minimum of

33ns before the next write sequence. The SCLK can be

either high or low between CS write pulses. Figure 1

shows the timing diagram for the complete 3-wire serial-

interface transmission.

Pin-/Software-Compatible,

16-/12-Bit, Voltage-Output DACs

10

______________________________________________________________________________________

24-BIT WORD

CONTROL BITS

DATA BITS

MSB

LSB

C7 C6 C5 C4 C3

C2

C1

C0 D15 D14 D13 D12 D11 D10 D9

D8

D7

D6–D0

DESC

FUNCTION

0

0

0

0

0

0

0

0

X

X

X

X

X

X

X

X

X

X

NOP

No operation.

0

0

0

0

0

0

0

1

XX

X

X

DAC

3

DAC

2

DAC

1

DAC

0

X

X

LDAC

Move contents of input

to DAC registers

indicated by 1’s. No

effect on registers

indicated by 0’s.

0

0

0

0

0

0

1

0

X

X

X

X

X

X

X

X

X

X

CLR

Software clear.

0

0

0

0

0

0

1

1

XX

X

X

DAC

3

DAC

2

DAC

1

DAC

0

READY_EN

X

Power

Control

Power down DACs

indicated by 1’s.

Set READY_EN = 1 to

enable READY.

0

0

0

0

0

1

0

1

0

0

0

0

0

0

LIN

0

0

0

Linearity Optimize DAC linearity.

0

0

0

1

DAC

3

DAC

2

DAC

1

DAC

0

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

Write

Write to selected input

registers (DAC output

not affected).

0

0

1

1

DAC

3

DAC

2

DAC

1

DAC

0

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

Write-

through

Write to selected input

and DAC registers,

DAC outputs updated

(writethrough).

0

0

1

0

0

0

0

0

X

X

X

X

X

X

X

X

X

X

NOP

No operation.

Table 1. Operating Mode Truth Table*

*

For the MAX5136/MAX5137, DAC2 and DAC3 do not exist. For the MAX5135/MAX5137, D0–D3 are don’t-care bits.