+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

8

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_______________Detailed Description

The MAX1245 analog-to-digital converter (ADC) uses a

successive-approximation conversion technique and

input track/hold (T/H) circuitry to convert an analog sig-

nal to a 12-bit digital output. A flexible serial interface

provides easy interface to microprocessors (µPs). No

external hold capacitors are required. Figure 3 is a

block diagram of the MAX1245.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog compara-

tor is illustrated in the equivalent input circuit (Figure 4). In

single-ended mode, IN+ is internally switched to

CH0–CH7, and IN- is switched to COM. In differential

mode, IN+ and IN- are selected from the following pairs:

CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure

the channels with Tables 2 and 3.

In differential mode, IN- and IN+ are internally switched

to either of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at

IN+ is sampled. The return side (IN-) must remain sta-

ble within ±0.5LSB (±0.1LSB for best results) with

respect to AGND during a conversion. To accomplish

this, connect a 0.1µF capacitor from IN- (the selected

analog input) to AGND.

During the acquisition interval, the channel selected as the

sition interval spans three SCLK cycles and ends on the

falling SCLK edge after the last bit of the input control

word has been entered. At the end of the acquisition inter-

sample of the signal at IN+.

The conversion interval begins with the input multiplexer

negative input, IN- (In single-ended mode, IN- is simply

COM). This unbalances node ZERO at the input of the

comparator. The capacitive DAC adjusts during the

remainder of the conversion cycle to restore node ZERO

to 0V within the limits of 12-bit resolution. This action is

DAC, which in turn forms a digital representation of the

analog input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of

conversion, the positive input connects back to IN+,

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

the signal, and is also the minimum time needed for the

signal to be acquired. It is calculated by:

INPUT

SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

OUTPUT

SHIFT

REGISTER

T/H

ANALOG

INPUT

MUX

12-BIT

SAR

ADC

IN

DOUT

SSTRB

DGND

AGND

SCLK

DIN

CH0

CH1

CH3

CH2

CH7

CH6

CH5

CH4

COM

VREF

OUT

REF

CLOCK

1

2

3

4

5

6

7

8

10

11

9

15

16

17

18

19

MAX1245

CS

SHDN

12, 20

14

13

Figure 3. Block Diagram

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

TRACK

T/H

SWITCH

12k

HOLD

12-BIT CAPACITIVE DAC

VREF

ZERO

COMPARATOR

–

+

16pF

SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit