2

TQ8105/TQ8106

PRELIMINARY DATA SHEET

For additional information and latest specifications, see our website: www.triquint.com

Figure 1. TQ8105 Block Diagram

The combination of a thermally enhanced, 100-pin

JEDEC, metric, plastic package, the low-power

dissipation of the device, and the wide case-

temperature range permits operation without a heat

sink in most designs.

The TQ8106 uses the same pinout as the TQ8105 and

is compatible with it.

The TQ8105/TQ8106 provides comprehensive,

integrated, loopback functionality and enhanced line

and reference clock diagnostics required of SONET/

SDH systems, minimizing additional external circuitry.

TQ8105/TQ8106 diagnostics include:

• Loss of Reference clock detector (LOR) output to

indicate that the PLL Reference Clock is not toggling

• Lock Indicator (RLOCK), which permits monitoring

of the receiver clock frequency, flagging when the

frequency drifts beyond approximately 500 ppm

• Loss of Signal (LOS) detector output to indicate that

the incoming data stream has no data transitions in

128-bit periods

• ECL/PECL input (NSOL) to allow LOS from an O/E

module to force the data stream to all zeroes,

eliminating the need for external glue logic.

CKSRC(2:0)

MXD(7:0)

TXD

TXCK

RXD

RXCK

2

2

2

2

ECL/

PECL

I/O

Block

DVPP

8

Parallel

to

Serial

DXD(7:0)

8

LBM(1:0)

2

PH(1:0)

2

Loop

Back &

Retime

Block

LOS

Detect

VPP

VNN

REFCKE

2

REFCKT

B

Y

A

B

Y

A

Clock

Data

Clock

Data

Clock

Data

Clock

Data

/8

Ext. Clk

11

Hold

Register

NOE

LOS

DXSYNC

OOF

Serial

to

Parallel

Clock

Phase

TxBC

RxBC

Framer

Clock/8

NRESET

3

PLL Clock

Synthesizer

NSOL

CLRLOS

Freq.

Lock

Detect

RLOCK

FRPWR

TQ8105