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TQ1090 Datasheet(PDF) 1 Page - TriQuint Semiconductor |
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TQ1090 Datasheet(HTML) 1 Page - TriQuint Semiconductor |
1 / 10 page T R I Q U I N T S E M I C O N D U C T O R , I N C . 1 For additional information and latest specifications, see our website: www.triquint.com TQ1090 11-Output Configurable Clock Buffer Figure 1. Block Diagram Output Buffers VCO Phase Detector VDD Q10 Q9 GND Q8 Q7 VDD TEST VDD Q0 GND Q1 Q2 VDD FBIN S1 REFCLK S0 GND GND GND GND Q3 Q4 VDD Q5 Q6 GND 1 2 14 13 12 11 10 9 87 6 5 4 3 22 21 20 19 18 17 16 15 27 28 25 24 23 26 MUX Divide Logic ÷ 2 Group A Group C Group B S1 S0 TriQuint’s TQ1090 is a configurable clock buffer which generates 11 outputs, operating over a wide range of frequencies from 33 MHz to 45MHz, 65 MHz to 90 MHz and 130 MHz to 180 MHz. The outputs are available at 1x, 2x and 4x, or at 1/2x, 1x and 2x, or at 1/4 x, 1/2 x and 1x the reference clock frequency, fREF. When one of the Group A outputs (Q0–Q4) is used as feedback to the PLL, all Group A outputs will be at fREF, all Group B outputs (Q5–Q8) will be at 2x fREF and all Group C outputs (Q9,Q10) will be at 4x fREF. When one of the Group B outputs is used as feedback to the PLL, all Group A outputs will be at 1/2 x fREF, all Group B outputs will be at fREF and all Group C outputs will be at 2x fREF. When one of the Group C outputs is used as feedback to the PLL, all Group A outputs will be at 1/4 x fREF, all Group B outputs will be at 1/2 x fREF and all Group C outputs will be at fREF. A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation. This completely self-contained PLL requires no external capacitors or resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency range from 260 MHz to 360 MHz. By feeding back one of the output clocks to FBIN, the PLL continuously maintains frequency and phase synchron- ization between the reference clock (REFCLK) and each of the outputs. Features • Wide frequency range: 33 MHz to 45 MHz 65 MHz to 90 MHz and 130 MHz to 180 MHz • Output configurations: four outputs at fREF four outputs at 2x fREF two output at 4x fREF or five outputs at 1/2 x fREF three outputs at fREF two outputs at 2x fREF • Selectable Phase Shift: –2t, –t, 0, +t (t = 1/fvco) • Low output-to-output skew: 150 ps (max) within a group • Near-zero propagation delay –350 ps ± 500 ps (max) or –350 ps ±700 ps (max) • TTL-compatible I/O with 30 mA output drive • Ideal for Power PC™ designs • 28-pin J-lead surface-mount package |
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