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ST7573 Datasheet(PDF) 11 Page - Sitronix Technology Co., Ltd. |
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ST7573 Datasheet(HTML) 11 Page - Sitronix Technology Co., Ltd. |
11 / 46 page ST7573 Ver 1.0b 11/46 2007/07/12 7. FUNCTIONS DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input The CSB pin is used for chip selection. ST7573 can interface with an MPU when CSB is "L". When CSB is “H”, the control pins (A0, /RD and /WR) are disabled and D0 to D7 are set to be high impedance. If using serial interface, the internal shift register and the counter are reset when CSB=”H”. Parallel / Serial Interface ST7573 has five types of interface to communicate with an MPU, which are three serial and two parallel interfaces. The parallel or serial interface is determined by PS[2:0] pin as shown below. Table 1 Parallel/Serial Interface Selection PS2 PS1 PS0 CSB A0 State “L” “L” “L” CSB A0 4 Pin-SPI MPU interface “H” “L” “L” CSB "H" 3 Pin-SPI MPU interface “L” “H” “L” CSB A0 8080-series parallel MPU interface “H” “H” “L” CSB A0 6800-series parallel MPU interface Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS[2:0] as shown in Table 2. The type of data transfer is determined by A0, ERD and RWR as shown in Table 3. Table 2 Microprocessor Selection for Parallel Interface PS2 PS1 PS0 CSB A0 ERD RWR DB0 to DB7 MPU bus H H L CSB A0 E R/W DB0 to DB7 6800-series L H L CSB A0 /RD /WR DB0 to DB7 8080-series Table 3 Parallel Data Transfer Common 6800-series 8080-series A0 E (/RD) R/W (/WR) /RD (E) /WR (R/W) Description H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction) NOTE: When ERD pin is always pulled high in 6800-series interface, the CSB can be used as enable signal. In this case, interface data is latched at the rising edge of CSB and the access type is determined by A0, RWR as 6800-series mode. Serial Interface ST7573 supports 3 kinds of serial interface and the type is selected by PS2~PS0 as shown below. Serial Mode PS2 PS1 PS0 CSB A0 4-line SPI interface L L L CSB A0 3-line SPI interface H L L CSB Not Used Fix to “H” |
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