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| ST7528 |
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 SITRONIX
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18 page 
ST7528 Ver2.3 18/97 2007/1/3 MICROPROCESSOR INTERFACE Microprocessor Interface Pin Description Name I/O Description RST I Reset input pin When RESETB is “L”, initialization is executed. PS[2:0] I Parallel / Serial data input select input PS2 PS1 PS0 Interface mode Data / Command Data Read/Write Serial clock L L H Parallel 80 A0 DB0 to DB7 RD / WR - L H H Parallel 68 A0 DB0 to DB7 E / RW - L L L 3Line Serial - SID (DB7) Write only SCLK (DB6) L H L 4Line Serial A0 SID (DB7) Write only SCLK (DB6) H L L IIC Serial - SDA Read/Write SCL *NOTE: In 4-Line, 3-Line and IIC serial mode, it is impossible to read data from the on-chip RAM. In 3-Line or 4-Line interface: DB0 to DB5, E_RD and RW_WR must be fixed to “H” or “L”. In IIC and 3-Line interface: A0 must be fixed to “H” or “L” Microprocessor interface select input pin − PS[2:0]=001: 8080-series parallel MPU interface − PS[2:0]=011: 68000-series parallel MPU interface − PS[2:0]=000: 3-Line-SPI MPU interface − PS[2:0]=010: 4-Line-SPI MPU interface − PS[2:0]=100: IIC-SPI MPU interface CSB I Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 may be high impedance. A0 I Register select input pin − A0 = "H": DB0 to DB7 are display data − A0 = "L": DB0 to DB7 are control data RW_WR I Read / Write execution control pin PS1 MPU type RW_WR Description H 6800-series RW Read / Write control input pin RW = “H” : read RW = “L” : write L 8080-series /WR Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal. |
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