2

Logic Analyzer Selection Guide for 16900 Series Mainframes

Agilent Model Number

16910A/16911A

16950B/16951B

16760A

Channels per module

102/68

68

34

Maximum channels on

510/340

340

170

single time base

Timing Mode

High-speed timing zoom [1]

4 GHz (250 ps) with 64 K depth

4 GHz (250 ps) with 64 K depth

N/A

Maximum timing sample

1.0 GHz (1 ns)

1.2 GHz (833 ps)

800 MHz

rate: half channel mode

Maximum timing sample

500 MHz (2.0 ns)

600 MHz (1.67 ns)

800 MHz

rate: full channel mode

Transitional timing

500 MHz (2.0 ns)

600 MHz (1.67 ns)

400 MHz

State Mode

Maximum state clock rate

450 MHz with option 500,

667 MHz

800 Mb/s (full channel),

250 MHz with option 250

1.5 Gb/s (half channel)

Maximum state data rate

500 Mb/s with option 500,

667 Mb/s (DDR)

1.5 Gb/s

250 Mb/s with option 250

1066 Mb/s (Dual Sample)

Setup/hold window

1.5 ns

1 ns (600 ps typical),

1 ns

Adjustment resolution

80 ps typical

80 ps typical

10 ps

State clock, data rate

Yes (Agilent E5865A for 16910A)

No

No

(upgradeable)

(Agilent E5866A for 16911A)

Automated threshold/sample

Yes

Yes

Yes

position, Simultaneous eye

diagrams, all channels

Memory Depth [2]

256 M

16951B

64 M

16950B, Option 064

16760A

32 M

Option 032

16950B, Option 032

16 M

Option 016

16950B, Option 016

4 M

Option 004

16950B, Option 004

1 M

Option 001

16950B, Option 001

256 K

Option 256

Memory depth

Yes (Agilent E5865A for 16910A)

Yes (Agilent E5875A)

64 M standard

(upgradeable)

(Agilent E5866A for 16911A)

Other

Supported signal types

Single-ended

Single-ended and differential

Single-ended and differential

Probe compatibility [3]

40-pin cable connector

90-pin cable connector

90-pin cable connector

Voltage threshold

–5 V to 5 V (10 mV increments)

–3 V to 5 V (10 mV increments)

–3 V to 5 V (10 mV increments)

Threshold Accuracy

±50 mV + 1% of setting

±30 mV ±2% of setting

±(30 mV + 1% of setting)

[1] All channels, all the time, simultaneous state and timing through same probe.

[2] Specify desired memory depth using available options.

[3] Probes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic analyzer and the device under test.