 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EM44CM1688LBA-25F Datasheet(PDF) 1 Page - Eorex Corporation |
|
||||||||||||||||||||||||||||||
EM44CM1688LBA-25F Datasheet(HTML) 1 Page - Eorex Corporation |
|
|
1 / 29 page  eorex EM44CM1688LBA Feb. 2009 www.eorex.com 1/29 1Gb (8M ×8Bank×16) Double DATA RATE 2 SDRAM Features • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 8 Banks • Posted CAS • Burst Length: 4 and 8. • Programmable CAS Latency (CL): 3, 4 and 5. • Programmable Additive Latency (AL): 0, 1, 2, 3 and 4. • Write Latency (WL) =Read Latency (RL) -1. • Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL) • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read. • On chip DLL align DQ, DQS and /DQS transition with CK transition. • DM mask write data-in at the both rising and falling edges of the data strobe. • Sequential & Interleaved Burst type available. • Off-Chip Driver (OCD) Impedance Adjustment • On Die Termination (ODT) • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms • Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C • RoHS Compliance • Partial Array Self-Refresh (PASR) • High Temperature Self-Refresh rate enable Description The EM44CM1688LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,741,824 bits which organized as 8Mbits x 8 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ. Available package: TFBGA-84Ball (13mmx9mm, 0.8mm x 0.8mm ball pitch). Ordering Information Part No Organization Max. Freq Package Grade Pb EM44CM1688LBA-25F 64M X 16 tCK 5: DDR2-800Mhz 5-5-5 ( Note ) TFBGA-84 Ball Commercial Free Note : Speed ( tCK *) is in order of CL-tRCD-tRP |
Similar Part No. - EM44CM1688LBA-25F |
|
Similar Description - EM44CM1688LBA-25F |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
