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LTC2355-14 Datasheet(PDF) 8 Page - Linear Technology |
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LTC2355-14 Datasheet(HTML) 8 Page - Linear Technology |
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8 / 18 page  LTC2355-12/LTC2355-14 2355fa pin Functions AIN+(Pin1):NoninvertingAnalogInput.AIN+operatesfully differentially with respect to AIN– with a 0V to 2.5V dif- ferential swing and a 0V to VDD common mode swing. AIN– (Pin 2): Inverting Analog Input. AIN– operates fully differentially with respect to AIN+ with a –2.5V to 0V dif- ferential swing and a 0V to VDD common mode swing. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor(or10µFtantaluminparallelwith0.1µFceramic). Can be overdriven by an external reference between 2.55V and VDD. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. VDD (Pin 7): 3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-State Serial Data Output. Each set of output data words represents the difference between AIN+ and AIN– analog inputs at the start of the previous conversion. SCK(Pin9):ExternalClockInput.Advancestheconversion process and sequences the output data on the rising edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or more SCK pulses wakes the ADC from sleep mode. CONV(Pin10):ConvertStart.Holdstheanaloginputsignal and starts the conversion on the rising edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses with SCK in fixed high or fixed low state start Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state start Sleep mode. Block Diagram 2355 BD – + 1 2 7 3 4 S & H GND EXPOSED PAD LTC2355-14 VREF 10µF AIN– AIN+ 14-BIT ADC 3.3V 10µF 14 8 10 9 THREE- STATE SERIAL OUTPUT PORT 2.5V REFERENCE TIMING LOGIC VDD SDO CONV SCK 5 6 11 |
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Similar Description - LTC2355-14 |
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