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MPC8548ECVUAQG Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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MPC8548ECVUAQG Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
9 / 144 page MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor 9 Overview — Single inbound doorbell message structure — Facility to accept port-write messages • PCI Express interface — PCI Express 1.0a compatible — Supports ×8, ×4, ×2, and ×1 link widths — Auto-detection of number of connected lanes — Selectable operation as root complex or endpoint — Both 32- and 64-bit addressing — 256-byte maximum payload size — Virtual channel 0 only — Traffic class 0 only — Full 64-bit decode with 32-bit wide windows • Pin multiplexing for the high speed I/O interfaces supports one of the following configurations: — ×8 PCI Express — ×4 PCI Express and 4× serial RapidIO • Power management — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle • System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the eight counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow • System access port — Uses JTAG interface and a TAP controller to access entire system memory map — Supports 32-bit accesses to configuration registers — Supports cache-line burst accesses to main memory — Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • JTAG boundary scan, designed to comply with IEEE Std. 1149.1™ |
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