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SPC5733MF0MMGA6 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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SPC5733MF0MMGA6 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 118 page  MPC5634M Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Overview Freescale Semiconductor 10 — Supports four external 8-to-1 muxes which can expand the input channel number from 31 to 59 • Two deserial serial peripheral interface modules (DSPI) —SPI – Full duplex communication ports with interrupt and DMA request support – Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family) – Support for queues in RAM – 6 chip selects, expandable to 64 with external demultiplexers – Programmable frame size, baud rate, clock delay and clock phase on a per frame basis – Modified SPI mode for interfacing to peripherals with longer setup time requirements – LVDS option for output clock and data to allow higher speed communication — Deserial serial interface (DSI) – Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO – 32 bits per DSPI module – Triggered transfer control and change in data transfer control (for reduced EMI) – Compatible with Microsecond Bus Version 1.0 downlink • Two enhanced serial communication interface (eSCI) modules — UART mode provides NRZ format and half or full duplex interface — eSCI bit rate up to 1 Mbps — Advanced error detection, and optional parity generation and detection — Word length programmable as 8, 9, 12 or 13 bits — Separately enabled transmitter and receiver — LIN support — DMA support — Interrupt request support — Programmable clock source: system clock or oscillator clock — Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0 • Two FlexCAN — One with 32 message buffers; the second with 64 message buffers — Full implementation of the CAN protocol specification, Version 2.0B — Based on and including all existing features of the Freescale TouCAN module — Programmable acceptance filters — Short latency time for high priority transmit messages — Arbitration scheme according to message ID or message buffer number — Listen only mode capabilities — Programmable clock source: system clock or oscillator clock — Message buffers may be configured as mailboxes or as FIFO • Nexus port controller (NPC) — Per IEEE-ISTO 5001-2003 — Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1 — Read and write access (Nexus class 3 feature that is supported on this device) – Run-time access of entire memory map – Calibration — Support for data value breakpoints / watchpoints – Run-time access of entire memory map – Calibration |
Similar Part No. - SPC5733MF0MMGA6 |
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Similar Description - SPC5733MF0MMGA6 |
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