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MPC8536ECVTAQG Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MPC8536ECVTAQG Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 128 page MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 Figure 1 shows the major functional units within the MPC8536E. Figure 1. MPC8536E Block Diagram 1 Pin Assignments and Reset States NOTE The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software NOTE The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to Table 1 for more details. e500 Core 32-Kbyte I-Cache 32-Kbyte D-Cache 64-bit DDR2/DDR3 SDRAM Controller with ECC Enhanced Local Bus Coherency Module Gigabit Ethernet DMA SEC OpenPIC eSPI DUART Async Performance Monitor Timers 512-Kbyte L2 Cache Power Management MPC8536E 2x I 2C Queue 8 Lane SERDES PCI 32 PCI-e PCI-e PCI-e SGMII SD MMC USB Host/ ULPI 2 Lane SERDES SATA Device USB Host/ ULPI Device USB Host/ ULPI Device w/ IEEE 1588 SATA Gigabit Ethernet SGMII w/ IEEE 1588 |
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