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MMA621010AEGR2 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MMA621010AEGR2 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 16 page MMA6222AEG Sensors 6 Freescale Semiconductor 1.4.11 ST This pin performs a dual function. When driven to a logic high level, the internal self-test voltage generator is activated. A low-to- high transition on this pin will clear the internal STATUS latch. Note that under certain fault conditions, the STATUS latch will be immediately reset, indicating a terminal fault condition. A diagram illustrating operation of the STATUS latch following device initialization is illustrated in Figure 1-5. Figure 1-5 ST and STATUS Interaction 1.4.12 CAP/HOLD When this input pin is low, acceleration data is updated by the DSP whenever a data sample becomes available. Upon a low-to- high transition of CAP/HOLD acceleration data is frozen. Acceleration data is not updated as long as the pin remains at a logic ‘1’ level. This pin may be tied directly to VSS if the hold function is not desired. 1.4.13 XOUT, YOUT Two digital-to-analog converters (DACs) are provided. These converters translate output of the DSP block into voltage levels pro- portional to the magnitude of the numerical result and ratiometric to VCC. 1.5 EXTERNAL COMPONENTS The connections illustrated in Figure 1-1 are recommended. Careful printed wiring board layout and component placement is es- sential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for the best performance. A grounded land area with solder mask should be placed under the package for improved shielding of the device from external effects. If a land area is not provided, no signals should be routed beneath the package. See Figure 1-1. ST FAULT DETECT SELF TEST ENABLE VDD D R Q STATUS |
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