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HT48RA5 Datasheet(PDF) 8 Page - Holtek Semiconductor Inc |
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HT48RA5 Datasheet(HTML) 8 Page - Holtek Semiconductor Inc |
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8 / 38 page  HT48RA5/HT48CA5 Rev. 1.40 8 May 22, 2009 sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad- dresses are stored). Data Memory - RAM The data memory is designed with 250 ´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (224 ´8). Most are read/write, but some are read only. The special function registers include the indirect ad- dressing registers (R0;00H, R1;02H), bank pointer (BP;04H), Timer/Event Counter 0 (TMR0;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 higher order byte register (TMR1H;0FH), Timer/Event Counter 1 lower order byte register (TMR1L;10H), Timer/Event Counter 1 control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register (STATUS; 0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O regis- ters (PA;12H, PB;14H, PC;16H, PF;1CH), and I/O con- trol registers (PAC;13H, PBC;15H, PCC;17H, PFC;1DH). The remaining space before the 20H is re- served for future expanded usage and reading these locations will get ²00H². The general purpose data memory, addressed from 20H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0 or MP1). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op- eration of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indi- rectly will return the result 00H. Writing indirectly results in no operation. The memory pointer registers (MP0 and MP1) are 8-bit registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location of the data memory and can carry out immediate data operations. The data move- ment between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Increment and decrement (INC, DEC) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the status register. G e n e r a l P u r p o s e D A T A M E M O R Y ( 2 2 4 B y t e s ) S p e c i a l P u r p o s e D A T A M E M O R Y 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H F F H : U n u s e d R e a d a s " 0 0 " 2 0 H I n d i r e c t A d d r e s s i n g R e g i s t e r 0 M P 0 I n d i r e c t A d d r e s s i n g R e g i s t e r 1 M P 1 B P A C C P C L T B L P T B L H W D T S S T A T U S I N T C T M R 0 T M R 0 C T M R 1 H T M R 1 L T M R 1 C P A P A C P B P B C P C P C C P F P F C T B H P RAM Mapping |
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