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MCIMX31LCJKN5D Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MCIMX31LCJKN5D Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 118 page  MCIMX31/MCIMX31L Technical Data, Rev. 4.3 10 Freescale Semiconductor Electrical Characteristics 4 Electrical Characteristics This section provides the device-level and module-level electrical characteristics for the MCIMX31. 4.1 Chip-Level Conditions This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference to the individual tables and sections. CAUTION Stresses beyond those listed under Table 5 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 8, "Operating Ranges," on page 13 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 4. MCIMX31 Chip-Level Conditions For these characteristics, … Topic appears … Table 5, “Absolute Maximum Ratings” on page 10 Table 7, “Thermal Resistance Data—19 × 19 mm Package” on page 11 Table 8, “Operating Ranges” on page 13 Table 9, “Specific Operating Ranges for Silicon Revision 2.0.1” on page 14 Table 10, “Interface Frequency” on page 14 Section 4.1.1, “Supply Current Specifications” on page 16 Section 4.2, “Supply Power-Up/Power-Down Requirements and Restrictions” on page 18 Table 5. Absolute Maximum Ratings Parameter Symbol Min Max Units Supply Voltage (Core) QVCCmax –0.5 1.65 V Supply Voltage (I/O) NVCCmax –0.5 3.3 V Input Voltage Range VImax –0.5 NVCC +0.3 V Storage Temperature Tstorage –40 125 oC ESD Damage Immunity: Vesd V Human Body Model (HBM) — 1500 Machine Model (MM) — 200 Charge Device Model (CDM) — 500 Offset voltage allowed in run mode between core supplies. Vcore_offset 1 1 The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4. —15 mV |
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