MMA81XXTKEG

Sensors

Freescale Semiconductor

3

SECTION 1 GENERAL DESCRIPTION

MMA81XXTKEG/MMA82XXTKEG family is a satellite accelerometer which is comprised of a single axis, variable capacitance

sensing element with a single channel interface IC. The interface IC converts the analog signal to a digital format which is trans-

mitted in accordance with the DSI-2.0 specification.

1.1

OVERVIEW

Signal conditioning begins with a Capacitance to Voltage conversion (C to V) followed by a 2-stage switched capacitor amplifier.

This amplifier has adjustable offset and gain trimming and is followed by a low-pass switched capacitor filter with Bessel function.

Offset and gain of the interface IC are trimmed during the manufacturing process. Following the filter the signal passes to the

output stage. The output stage sensitivity incorporates temperature compensation.

The output of the accelerometer signal conditioning is converted to a digital signal by an A/D converter. After this conversion the

resultant digital word is converted to a serial data stream which may be transmitted via the DSI bus. Power for the device is

integrated regulator supplies fixed voltage to internal circuitry.

A self-test voltage may be applied to the electrostatic deflection plate in the sensing element. Self-Test voltage is factory trimmed.

Other support circuits include a bandgap voltage reference for the bias sources and the self-test voltage.

A total of 128 bits of One-Time Programmable (OTP) memory, are provided for storage of factory trim data, serial number and

device characteristics. Eighty OTP bits are available for customer programming. These eighty OTP bits may be programmed via

the DSI Bus or through the serial test/trim interface. OTP integrity is verified through continuous parity checking. Separate parity

bits are provided for factory and customer programmed data. In the event that a parity fault is detected, the reserved value of

zero is transmitted in response to a Read Acceleration Data command.

A block diagram illustrating the major elements of the device is shown in Figure 1-1.