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78P2352 Datasheet(PDF) 11 Page - Teridian Semiconductor Corporation |
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78P2352 Datasheet(HTML) 11 Page - Teridian Semiconductor Corporation |
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11 / 42 page  78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Page: 11 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (CONTINUED) ADDRESS 0-1: INTERRUPT CONTROL REGISTER This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as required. BIT NAME TYPE DFLT VALUE DESCRIPTION 7 INPOL R/W 0 Interrupt Pin Polarity Selection: 0 : Interrupt output is active-low (default) 1 : Interrupt output is active-high 6:2 -- R/W 01000 Reserved for future use 1 MTLOL R/W 1 TXLOL Error Mask (active low): Gates the TXLOL register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass 0 MFERR R/W 1 FIERR Error Mask (active low): Gates the respective FIERR register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass ADDRESS 0-2: RESERVED BIT NAME TYPE DFLT VALUE DESCRIPTION 7:0 -- R/W XXXXXXX0 Reserved. |
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