1

2

3

DSG

4

BAT

5

6

VC2

7

VC3

8

VC4

9

10

SRP

CHG

PACK

ZVCHG

24

FUSE

23

REG27

22

VSS

21

VC1

11

SRN

12

TS1

TS2

NC

RBI

20

19

PRES

18

SMBC

17

NC

16

SMBD

15

14

13

NC

NC

bq3060

SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009

www.ti.com

PIN DETAILS

TSSOP (PW)

(TOP VIEW)

Table 2. Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

BAT

1

P

Power input from battery

DSG

2

O

P-CH FET Drive controlling discharge

Sense voltage input terminal and external cell balancing drive output for most positive cell, and

VC1

3

IA

battery stack measurement input.

Sense voltage input terminal and external cell balancing drive output for second most positive

VC2

4

IA

cell.

VC3

5

IA

Sense voltage input terminal and external cell balancing drive output for third most positive cell.

VC4

6

IA

Sense voltage input terminal and external cell balancing drive output for least positive cell.

Analog input pin connected to the internal coulomb-counter peripheral for integrating a small

SRP

7

IA

voltage between SRP and SRN where SRP is the top of the sense resistor.

Analog input pin connected to the internal coulomb-counter peripheral for integrating a small

SRN

8

IA

voltage between SRP and SRN where SRN is the bottom of the sense resistor.

TS1

9

I/O,IA

Thermistor input TS1

TS2

10

I/O,IA

Thermistor input TS2

NC

11

-

Keep this pin floating

NC

12

-

Keep this pin floating

NC

13

-

Keep this pin floating

SMBD

14

I/OD

SMBus data pin

NC

15

-

Keep this pin floating

SMBC

16

I/OD

SMBus clock pin

PRES

17

I/OD

Active low input to sense system insertion and typically requires additional ESD protection

RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily

RBI

18

P

lost by using a capacitor attached between RBI and VSS

VSS

19

P

Device ground

REG27

20

P

Internal power supply 2.7V bias output

FUSE

21

I/OD

Push-pull fuse drive and secondary protector activation input sensing

ZVCHG

22

O

P-CH precharge FET Drive controlling pre-charge and zero-volt charge

CHG

23

O

P-CH FET Drive controlling charge

PACK

24

P

PACK positive terminal and alternative power source

4

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): bq3060