CY14B256LA
Document Number: 001-54707 Rev. *B
Page 4
Table 1. Pin Definitions
Pin Name
I/O Type
Description
A0 – A14
Input
Address Inputs Used to Select One of the 32,768 bytes of the nvSRAM.
DQ0 – DQ7 Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power
Supply
Power Supply Inputs to the Device. 3.0V +20%, –10%
HSB
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
VCAP
Power
Supply
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No Connect No Connect. This pin is not connected to the die.
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