11 / 26 page
CY14B256KA
Document #: 001-55720 Rev. *A
Page 11 of 26
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can
be used to generate an interrupt. These flags are set by the
watchdog timeout, alarm match, or power fail monitor respec-
tively. The processor can either poll this register or enable inter-
rupts to be informed when a flag is set. These flags are automat-
ically reset when the register is read. The flags register is
automatically loaded with the value 0x00 on power up (except for
the OSCF bit; see Stopping and Starting the Oscillator on page
9).
Figure 4. RTC Recommended Component Configuration
Figure 5. Interrupt Block Diagram
Xout
Xin
Y1
C2
C1
Recommended Values
Y1 = 32.768 KHz (12.5 pF)
C1 = 10 pF
C2 = 67 pF
Note: The recommended values for C1 and C2 include
board trace capacitance.
Watchdog
Timer
Power
Monitor
Clock
Alarm
VINT
WDF
WIE
PF
PFE
AF
AIE
P/L
Pin
Driver
H/L
INT
VCC
VSS
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Enable
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
