NCP5393B

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6

NCP5393B PIN DESCRIPTIONS

Pin No.

Description

Symbol

32

NB_DROOP

Voltage output signal proportional to total current drawn from the VDDNB regulator. Used when load

line operation (“droop”) is desired.

33

NB_FB

34

NB_COMP

35

VID0

Parallel Voltage ID DAC Input 0. Not used in SVI mode.

36

VID1

Parallel Voltage ID DAC Input 1. Also used for PVI or SVI mode selection.

37

PWROK

System power supplies status input. Used in SVI mode only.

38

ENABLE

High = Run, Low = Standby/Reset.

39

VID3/SVC

Parallel Voltage ID DAC Input 1. Also used in SVI mode.

40

VID2/SVD

Parallel Voltage ID DAC Input 1. Also used in SVI mode.

41

PWRGOOD

Open drain output. High indicates that the active output(s) are within specification. Internally pulled

42

NB_DRVON

43

DRVON

44

NB_G

45

G4

PWM output #4. See Table: “Pin Connections vs. Phase Count”

46

G3

PWM output #3. See Table: “Pin Connections vs. Phase Count”

47

G2

PWM output #2. See Table: “Pin Connections vs. Phase Count”

48

G1

PWM output #1. See Table: “Pin Connections vs. Phase Count”

FLAG

PGND

High−current power supply return via metal pad (flag) underneath package. The package flag should

be tied directly to Pin 2.

PIN CONNECTIONS VS. PHASE COUNT

Number of

Phases

G4

G3

G2

G1

CS4 &

CS4N

CS3 &

CS3N

CS2 &

CS2N

CS1 &

CS1N

4

Phase 4

Out

Phase 3

Out

Phase 2

Out

Phase 1

Out

Phase 4 CS

Input

Phase 3 CS

Input

Phase 2 CS

Input

Phase 1 CS

Input

3

Tie to

GND

Phase 3

Out

Phase 2

Out

Phase 1

Out

Tie to GND

Phase 3 CS

Input

Phase 2 CS

Input

Phase 1 CS

Input

2

Tie to

GND

Phase 2

Out

Tie to

GND

Phase 1

Out

Tie to GND

Phase 2 CS

input

Tie to GND

Phase 1 CS

Input