NB7VQ58M

http://onsemi.com

2

VT1 SEL EQEN VCC

VT0 GND GND

Q

GND

GND

Q

IN0

IN0

IN1

IN1

56

7

8

16

15

14

13

12

11

10

9

1

2

3

4

NB7VQ58M

Exposed

Pad (EP)

VCC

Q

Q

75 kW

IN0

IN0

VT0

IN1

IN1

VT1

SEL

Multi−Level Inputs

LVPECL, LVDS, CML

Figure 2. Detailed Block Diagram

50 W

50 W

50 W

50 W

EQ

0

1

2:1

Mux

0

1

2:1

Mux

75 kW

EQEN

(Equalizier Enable)

VCC

GND

Table 1. EQualizer ENable FUNCTION

EQEN

Function

0

INn / INn Inputs By−pass the EQualizer section

1

Inputs flow through the EQualizer

Table 2. SELect FUNCTION TRUTH TABLE

SEL

Q

Q

L

D0

D0

H

D1

D1

Table 3. PIN DESCRIPTION

Pin

Name

I/O

Description

1

IN0

LVPECL, CML, LVDS Input

Noninverted Differential Input (Note 1)

2

IN0

LVPECL, CML, LVDS Input

Inverted Differential Input (Note 1)

3

IN1

LVPECL, CML, LVDS Input

Noninverted Differential Input (Note 1)

4

IN1

LVPECL, CML, LVDS Input

Inverted Differential Input (Note 1)

5

VT1

−

Internal 50 W Termination Pin for IN1/IN1

6

SEL

LVTTL/LVCMOS Input

SEL Input. Low for IN0 inputs, High for IN1 inputs. (Note 1) Pin will default HIGH when

left open (has internal pullup resistor)

7

EQEN

LVCMOS Input

Equalizer Enable Input; pin will default LOW when left open (has internal pulldown

resistor)

8

VCC

−

Positive Supply Voltage (Note 2)

9

Q

CML Output

Inverted Differential Output

10

GND

−

Negative Supply Voltage

11

GND

−

Negative Supply Voltage

12

Q

CML Output

Noninverted Differential Output

13

VCC

−

Positive Supply Voltage (Note 2)

14

GND

−

Negative Supply Voltage

15

GND

−

Negative Supply Voltage

16

VT0

−

Internal 50 W Termination Pin for IN0/IN0

−

EP

−

The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die

for improved heat transfer out of package. The exposed pad must be attached to a

heat−sinking conduit. The pad is electrically connected to the die, and must be

electrically and thermally connected to GND on the PC board.

1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and

if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source

termination resistors.

2. All VCC and GND pins must be externally connected to a power supply for proper operation.