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NB6HQ14MMNHTBG Datasheet(PDF) 3 Page - ON Semiconductor |
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NB6HQ14MMNHTBG Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 11 page NB6HQ14M http://onsemi.com 3 EQEN Q3 Q3 VCCO GND Q0 Q0 VCC Q1 Q1 Q2 Q2 IN VT VREFAC IN 56 7 8 16 15 14 13 12 11 10 9 1 2 3 4 NB6HQ14M Exposed Pad (EP) Figure 2. QFN−16 Pinout (Top View) Table 1. EQUALIZER ENABLE FUNCTION EQEN Function 0 IN / IN Inputs By−pass the Equalizer section 1 Inputs flow through the Equalizer Table 2. PIN DESCRIPTION Pin Name I/O Description 1 IN LVPECL, CML, LVDS Input Non−inverted Differential Input. Note 1. 2 VT Internal 100 W Center−tapped Termination Pin for IN / IN 3 VREFAC Output Voltage Reference for Capacitor−Coupled Inputs, only 4 IN LVPECL, CML, LVDS Input Inverted Differential Input. Note 1. 5 EQEN LVCMOS Input Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor) 6 Q3 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 7 Q3 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 8 VCCO − 1.8 V or 2.5 V Positive Supply Voltage for the Qn / Qn CML Outputs 9 Q2 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 10 Q2 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 11 Q1 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 12 Q1 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 13 VCC − 2.5 V Positive Supply Voltage for the core 14 Q0 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 15 Q0 CML Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 16 GND − Negative Supply Voltage − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally con- nected to GND on the PC board. 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN / IN input, then, the device will be susceptible to self−oscillation. 2. All VCC, VCCO and GND pins must be externally connected to a power supply for proper operation. |
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