Monitor Input (IN)

Connect the center point of a resistive divider to IN to

monitor external voltages (see R1 and R2 of the Typical

0.5V and a falling threshold of 0.495V (5mV hysteresis).

ENABLE is low) OUT goes high (OUT goes low) after

0.495V, OUT goes low (OUT goes high) after a 16µs

delay. IN has a maximum input current of 15nA so

large-value resistors are permitted without adding sig-

nificant error to the resistive divider.

Adjustable Delay (CDELAY)

low), the internal 250nA current source begins charging

an external capacitor connected from CDELAY to GND.

When the voltage at CDELAY reaches 1V, the output

asserts (OUT goes high or OUT goes low). When the

high (OUT going low) according to the equation:

to GND.

0.5V and ENABLE goes from low to high (ENABLE

period. For nonadjustable delay devices (P version)

there is a 1µs propagation delay from when the enable

input is asserted to when the output asserts. Figures 2

through 5 show the timing diagrams for the adjustable

and fixed delay versions, respectively.

Ultra-Small, Adjustable

Sequencing/Supervisory Circuits

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7

Figure 2. MAX6895A/MAX6897A Timing Diagram

IN

ENABLE

OUT