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QHX220ICT7 Datasheet(PDF) 5 Page - Intersil Corporation |
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QHX220ICT7 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 19 page  5 FN6986.0 October 20, 2009 SPI Bus Characteristics FIGURE 2. SPI BUS TIMING DIAGRAM BUSENBAR CLK DATA 24BIT Data register lock MSB LSB TDS TDH TCP TBEB2C TC2BEB TCH TCL SPI BUS TIMING REQUIREMENT SYMBOL PARAMETER MIN TYP MAX tCP SPI clock period 100ns tCL Clock pulse width low 40ns tCH Clock pulse width high 40ns tBEB2C BUSENBAR Fall to CLK Rise Setup Time 5ns tC2BEB CLK Rise BUSENBAR Fall Delay 40ns tDS Data Setup Time 20ns tDH Data Hold Time 0ns TABLE 1. SPI BUS DATA FORMAT 10BIT I-DAC <23:14> 10BIT Q-DAC <13:4> FREQ RANGE <3:2> GAIN <1> SPARE <0> QHx220 |
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